1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method of forming and removing spacer layers upon and from, respectively, sidewall surfaces of a gate conductor and substrate proximate to the gate conductor. An etch stop layer formed upon the gate conductor and substrate serves to protect, during spacer formation, against overetch into the underlying gate conductor and substrate.
2. Description of Related Art
Fabrication of a metal-oxide semiconductor ("MOS") transistor is well known. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas on the semiconductor substrate by various isolation structures formed upon and within the substrate. Isolation structures come in many forms. For example, the isolation structures can be formed by etching trenches into the substrate and then filling the trenches with a dielectric fill material. Isolation structures may also be formed by locally oxidizing the silicon substrate using the well recognized LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in, for example, an oxidation furnace or a rapid thermal annealer ("RTA"). A gate conductor material is then deposited across the entire dielectric-covered substrate. The gate conductor material is preferably polycrystalline silicon, or polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the "develop" stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
The patterned gate conductor material, if polysilicon, is rendered conductive with the introduction of ions from an implanter or a diff-usion furnace. Depending on the implant species forwarded into the gate conductor, either an n-channel transistor (NMOS transistor) or a p-channel transistor (PMOS transistor) is formed. NMOS transistors employ n-type dopants on opposite sides of the NMOS gate conductor, whereas PMOS transistors employ p-type dopants on opposite sides of the PMOS transistor gate conductor. The regions of the substrate which receive dopants on opposite sides of the gate conductor are generally referred to as junction regions, and a distance between junction regions is typically referred to as the physical channel length. After implantation and subsequent diffusion of the junction regions, the distance between the junction regions becomes less than the physical channel length and is often referred to as the effective channel length ("Leff"). In high density designs, not only does the physical channel length become small so to must the Leff As Leff decreases below approximately 1.0 .mu.m, for example, a problem known as short channel effects ("SCE") becomes predominant.
A problem related to SCE, and the subthreshold currents associated therewith, but altogether different is the problem of hot-carrier effects ("HCE"). HCE is a phenomenon by which hot-carriers ("holes and electrons") arrive at or near an electric field gradient. The electric field gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent to the channel. The electric field at the drain causes primarily electrons in the channel to gain kinetic energy and become "hot". These hot electrons traveling to the drain lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its Leff is less than, e.g., 0.8 .mu.m.
Unless modifications are made to the process in which relatively small transistors are formed, problems with sub-threshold current and threshold shift resulting from SCE and HCE will remain. To overcome these problems, alternative drain structures such as double-diffused drain ("DDD") and lightly doped drain ("LDD") structures must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce Em. The popularity of DDD structures has given way to LDD structures since DDD causes unacceptably deep junctions and deleterious junction capacitance.
A conventional LDD structure is one whereby a light concentration of dopant is self-aligned to the edge of the gate conductor. The light-dopant concentration is then followed by a heavier-dopant concentration which is self-aligned to a spacer formed on the sidewalls of the gate conductor. The purpose of the first implant dose is to produce a lightly doped section into the junction areas at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. Resulting from the first and second implants, a dopant gradient occurs across the junction from the source/drain area of the junction to the LDD area adjacent the channel.
A conventional spacer is one which is generally formed by a single deposition, followed by a single anisotropic etch. The spacer therefore comprises a single layer of material formed on sidewall surfaces of the gate conductor. Resulting from the single spacer construction, an LDD area is defined immediately below that spacer adjacent the channel. The source/drain region is spaced from the channel a distance dictated by the LDD area. While the LDD area serves to reduce HCE, it nonetheless proves detrimental to the performance of the ensuing transistor. This detriment is the result of added parasitic resistance arising from the lightly doped LDD region. Added parasitic resistance typically decreases saturation current (i.e., current above threshold). Further, parasistic resistance can decrease drive strength and the overall speed of the transistor.
In most integrated circuit applications there are transistors which are required to be high performance transistors. In those instances, high performance transistors should have minimal LDD areas if any at all. The lower performing transistors should have larger LDD areas so they do not suffer HCE reliability problems. It would therefore be desirable to derive a fabrication technique whereby certain transistors within an integrated circuit employ larger LDD areas than other transistors. The integrated circuit formed by such a process would be tailored with LDD regions specifically designed to the performance of the transistor being produced. The junction region of each transistor within the monolithic circuit could therefore be customized to a particular dopant concentration profile and peak concentration depth depending upon the performance desired.